Description: Unlocking the Phase Locked Loop (PLL) – Part 1
At first glance, this tutorial seemed promising but as I looked more closely, several issues arose.
1. The phase detector gain, defined on page 1, is sometimes designated as K-sub-m, sometimes as K-sub-d, sometimes as k-sub-d, sometimes as k-sub-m (see pages 1,2,5,9).
2. Sometimes omega is used to designate angular frequency, sometimes “w” (page 2).
3. On page 5, paragraph below Fig 7, you state “… 90 phase difference which is required to make this whole thing work”. If this true, you should also tell the reader why it would fail.
4. I don’t see the point of Figs 8-13 and feel they may introduce confusion. I say this because they show possible error signals that converge to non-zero values. In a properly operating PLL, errors should instead approach zero, as you state on page 7.
5. On page 8, the top 3 equations used different subscripts on omega: “i”, “c”, and “out”. If s-sub-2() is the output of the VCO, shouldn’t that omega be omega-sub-out? Also, in the expression for omega-sub-out, shouldn’t omega-sub-i be the input?
6. On page 8, you state the K-sub-0 has units of Hz per volt however you defined it in terms of omega which has units of radians per volt.
7. On the page, the equality at the top of the page makes no sense- I assume phi-of-t was meant.
8. On page 9, the expression for phi-sub-2 comes out of nowhere. You do not explain why you can replace frequency with s-sub-e, something you said earlier is not frequency dependent.
Page 9 is as far as I got in the tutorial. I still think this could be useful if the details get cleaned-up and the organization improved.
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