Firstly I really appreciate your great tutorial. According to page 11, last paragraph describing how to encode 1101 using the state diagram, my question is why do we start from the MSB( from left to right)? like you wrote the arrival of 1 and then 0 and then 1 and finally 1?

Thanks for the tutorial….How to make trellis diagram for 2/3 or 3/4 etc convolution encoder…
i.e. how to make trellis diagram when input bit is more than one…as this is used in TCM

No other author has explained the coding and decoding theory with so much of clarity. One small clarification. The tree diagram on Page:13; 11(100)up 11(011) up 01(010) may have to be corrected as 11(100)up 11(010) up 01(001). Regret if I am giving a wrong suggestion.

Yes, you are correct. Need to go back and fix it. I am busy trying get my book out so it might be while.
Thank you very much for you comments, however.

I can see your frustration, however this document was done a long time ago. I no longer have the files to change it.
I have marked the figure where the bits should be changed. Hope that helps.

Referring to the list of generator polynomials given on page 2. The number of binary bits for both G1 and G2 for a given constraint length are not matching. Why is this so?

after reading a lot , i cant find how connections ( basically I/Ps ) to modulo-2 adders are decided , you mentioned that Peterson and weldon mentioned about how to decide the Polynomial , but i cant find that,so can you plz let me know how polynomials (i.e which Shift registers output will go to which Modulo adder and how they are connected.

Let’s say the polynomial is x^2 + x^3
Then the coefficients are 0, 1, 1. Now 0 being the coefficient of the linear term x, 1 being the coefficient of two next polynomials x^2 and x^3. Then these are your connections.
Its really quite simple.
Charan Langton
PS I have already given a list of “good” polynomials in the tutorial.

I think I found a typo on Pg-12, Tree Diagrams section: Ref. Fig-9, at the first coding step, the output is 11 and the new state is 100. However, the text says ‘111’.

For the ‘decoding using a sequential algorithm’,I get confused about the error counter.
Since for the decoder, it can not know the real information bit which has been transmitted.
So, how you know it is error when you decode and increase the error count?

There are only specific transitions that can happen. For example, if the current bit set is 00 and then we get 01 and the transition does not allow that, then we know an error has occurred either in the current set of bits or some where earlier.

Consider a (2,1,4) code as mentioned in the document.

There are four registers and the Constraint length is 1 x ( 4 – 1 ) = 3

We need a total of four connections from the registers to the adders.

However, the table in page 2 show only 3 digits for the constraint length. In addition the connections for the (2,1,4) code generator in the next page doesn’t match up with connections mentioned in the table. Can you please clarify.

I believe figure 6c and 6d should have input=0 in the caption rather than input=1. Also in 6d, the input state should be 001. Unless I miss something!

By the way, I really appreciate your tutorials. Very well written and intuitive! Many thanks.

Firstly I really appreciate your great tutorial. According to page 11, last paragraph describing how to encode 1101 using the state diagram, my question is why do we start from the MSB( from left to right)? like you wrote the arrival of 1 and then 0 and then 1 and finally 1?

Regards

Damoon

Thanks for the tutorial….How to make trellis diagram for 2/3 or 3/4 etc convolution encoder…

i.e. how to make trellis diagram when input bit is more than one…as this is used in TCM

No other author has explained the coding and decoding theory with so much of clarity. One small clarification. The tree diagram on Page:13; 11(100)up 11(011) up 01(010) may have to be corrected as 11(100)up 11(010) up 01(001). Regret if I am giving a wrong suggestion.

Yes, you are correct. Need to go back and fix it. I am busy trying get my book out so it might be while.

Thank you very much for you comments, however.

How can we have input bit of one (1) , when u actually input zero (0) – this document is riddled with errors

I can see your frustration, however this document was done a long time ago. I no longer have the files to change it.

I have marked the figure where the bits should be changed. Hope that helps.

very short and impressive note. Thank you!

Referring to the list of generator polynomials given on page 2. The number of binary bits for both G1 and G2 for a given constraint length are not matching. Why is this so?

after reading a lot , i cant find how connections ( basically I/Ps ) to modulo-2 adders are decided , you mentioned that Peterson and weldon mentioned about how to decide the Polynomial , but i cant find that,so can you plz let me know how polynomials (i.e which Shift registers output will go to which Modulo adder and how they are connected.

Let’s say the polynomial is x^2 + x^3

Then the coefficients are 0, 1, 1. Now 0 being the coefficient of the linear term x, 1 being the coefficient of two next polynomials x^2 and x^3. Then these are your connections.

Its really quite simple.

Charan Langton

PS I have already given a list of “good” polynomials in the tutorial.

I think I found a typo on Pg-12, Tree Diagrams section: Ref. Fig-9, at the first coding step, the output is 11 and the new state is 100. However, the text says ‘111’.

Many thanks for this lucid tutorial.

For the ‘decoding using a sequential algorithm’,I get confused about the error counter.

Since for the decoder, it can not know the real information bit which has been transmitted.

So, how you know it is error when you decode and increase the error count?

There are only specific transitions that can happen. For example, if the current bit set is 00 and then we get 01 and the transition does not allow that, then we know an error has occurred either in the current set of bits or some where earlier.

I don’t quite understand the Figure 3 on the subject of “Punctured Codes”. Is there a mistake?

I thought getting 2 inputs should mean 2 different inputs as in the diagram as u1 & u2.

Outputs are v1, v2 and “v3”?

What am I not understanding?

Thank you,

Consider a (2,1,4) code as mentioned in the document.

There are four registers and the Constraint length is 1 x ( 4 – 1 ) = 3

We need a total of four connections from the registers to the adders.

However, the table in page 2 show only 3 digits for the constraint length. In addition the connections for the (2,1,4) code generator in the next page doesn’t match up with connections mentioned in the table. Can you please clarify.